1. Field of the Invention
The invention generally relates to integrated circuit input/output (I/O) buffers, and more particularly relates to techniques for minimizing the effects of switching noise.
2. Prior Art
Due to advances in technology, integrated circuits can now operate at extremely high speeds (e.g., very small response time between a change at the input and a corresponding change at the output). At these high speeds, switching noises can cause adverse effects on the power supply stability of integrated circuits. The reason is power and ground lines in integrated circuits have inherent inductances. For example, during switching from low to high and vice versa of a complementary metal oxide semiconductor (CMOS) integrated device, current is required to charge and discharge the device capacitive load which results in a change in current flow. Such current changes produce a voltage across the inductances inherent in power and ground lines. Consequently, a "voltage droop" may occur in the power voltage (Vdd) and/or a "ground bounce" may occur in the source voltage (Vss) during switching. These voltage spikes can result in erroneous data transitions. Additionally, by reducing the voltage operating range, voltage spikes can cause undesirable operating delays.
The adverse effects caused by voltage spikes are particularly prevalent when multiple circuits, such as I/O buffer circuits, share the same ground line and power line. As an example, while some I/O buffer circuits may undergo simultaneous switching from high to low, other I/O buffer circuits may remain unswitched by design. When the simultaneous switching I/O buffers changes from high to low, a relatively large current flows through the common ground line to turn the switching I/O buffers off. The change of current flow coupled with the ground line's inherent inductance causes a ground bounce which may turn the unswitched I/O buffers on erroneously.
One solution to minimize voltage spikes caused by switching noise is to replace the single large current surge that occurs during switching with smaller current surges at different times. The embodiments of the above solution are described in U.S. Pat. No. 5,426,376 and its continuation-in-part U.S. Pat. No. 5,534,791 which are assigned to VLSI Technology, Inc, the same assignee for the present invention. As described by U.S. Pat. No. 5,534,791 and U.S. Pat. No. 5,426,376, the task of replacing one single large current surge by smaller current surges at different times can be accomplished by providing within each I/O buffer two separate drivers: a Transient Switching Circuit (TSC) (hereinafter AC driver) and a Logic Holding Circuit (LHC) (hereinafter DC driver). Generally, the AC driver is operational from a time just after the occurrence of a transition on the input signal of the I/O buffer to a time prior to when the rail voltage is reached. Conversely, the DC driver is operational from a time just prior to when the AC driver turns off to a time at which a subsequent logic transition occurs at the input signal. Hence, the operational phases of the AC and DC drivers have a little overlap.
While the I/O buffer circuit in U.S. Pat. No. 5,426,376 can be used in either shared power bus or separate power bus arrangements, the I/O buffer circuit in U.S. Pat. No. 5,534,791 is used in a separate power bus arrangement. In other words, the invention in U.S. Pat. No. 5,534,791 has separate power and ground sources for its AC and DC driver circuits. In a separate power bus arrangement, voltage spikes caused by switching noise can be best minimized by not turning the DC driver on until the output transition is substantially complete and the AC driver has been or is about to be turned off. In doing so, the combined effects of switching noises from the AC and DC drivers are minimized.
Moreover, the effects of switching noise are further minimized, as described by U.S. Pat. No. 5,534,791, by making the DC driver independent of the output voltage after the DC driver has been activated. In doing so, voltage oscillations at the output terminal can be prevented from causing the DC driver to switch on and off erroneously. The I/O buffer circuit in U.S. Pat. No. 5,534,791 achieves these objectives. However, I/O buffer in U.S. Pat. No. 5,534,791 requires 32 transistors. In integrated circuits design, an important consideration is the optimum number of transistors required in a device. The reason is extra transistors mean additional manufacturing costs as well as less space for implementing additional functions. This has added importance given the number of devices in a typical integrated circuit.
Thus, a need exists for an I/O buffer with a minimized footprint, which is less susceptible to voltage spikes caused by switching noise and which is adapted for use in a separate power bus arrangement.